High-Speed SerDes Applications Engineer

Rambus (now Cadence), Toronto

Worked with analog designers on RX PLE design verification for 22nm multi-protocol SerDes IP
Gained familiarity with the functionality of various SerDes sub-blocks such as LC and RPLLs, CDR, CTLE, CMU, Lane TX/RX architecture etc.
Streamlined SerDes IBIS-AMI simulations, DPI/CPU simulations, and PI simulations for various PCIe IPs
Proactively managed client relations and served a diverse clientele across 3 continents spanning from start-ups to Fortune 500 companies, with a focus on multiple sectors including Military, Space, and Data Centers
Demonstrated a consistent track record of debugging complex SerDes customer issues in a constrained timeframe and with limited information. Accumulated 1900+ hours of SerDes client interaction

Designed low-power electronics for cutting-edge fitness products such as smartwatches and cycling sensors used by professional athletes globally
Developed an in-house battery characterization tool that streamlined testing processes across Garmin fitness product lines, reducing testing time by 75% while allowing for more in-depth battery analysis
Led simulation, schematic, and layout reviews for upcoming products
Effectively communicated design constraints (part cost, component placement, design time, materials, and manufacturing etc.) to other engineering teams, managers, silicon vendors and manufacturing facilities
Successfully onboarded and mentored the incoming intern
Link to a Garmin product that I designed: Garmin Powered Mount

Developed Python scripts for Alberta’s electrical grid maintenance, reducing 4.1 months of manual work to 2 hours